// ==================== part-select ====================
assign val[i] = a[i*4+:4]; //equal to assign val[i] = a[i*4+3:i*4]

// ==================== generate ====================
genvar 			 i;
generate
//   genvar 			 i;
   for(i=0;i<9;i++)
     begin : mul_pps
	booth2_pp_gen #(16+1) unit // visit by mul_pps[i].unit.xxx
	 (
	  .o_pp(pp[i]),
	  .o_pp_s(S[i]),
	  .o_pp_e(E[i]),
	  .i_mcand(a_16),
	  .i_booth2(b_16_ext[i*2+2:i*2])
	  );
     end
endgenerate


generate
   genvar 			i;
   for(i=0;i<STAGE;i++)
     begin
	logic xxx;		// internal nets
	always_ff@(posedge `FSE_TOP.clk) // always block
	  begin
	     if(`FSE_TOP.pipeline_stage_en[i])
	       sn_ps_r[i+1] <= sn_ps_r[i];
	  end
	assign result[i] = xxx;	// assign
     end
endgenerate






// === (used for sim) and ==
module tb();
   logic [7:0] ta, tb;
   initial
     begin
	ta = 8'h1x;
	tb = 8'h1x;
	
	if(ta == tb)		// the result of compare is X which treated as false, so neither "equal" nor "no equal" (else valid)
	  $display("ta == tb");
	else
	  $display("ta == tb not met");
	
	if(ta != tb)
	  $display("ta != tb");
	else
	  $display("ta != tb not met");

	if(ta === tb)
	  $display("ta === tb");
	
	if(ta !== tb)
	  $display("ta !== tb");
     end
endmodule



// write file
integer logfile;
logfile = $fopen("log", "w");
$fdisplay(logfile, "hello");

  